Le principe de calcul stochastique appliqué au décodage des turbocodes : conception, implémentation et prototypage sur circuit FPGA

The publication of turbo codes in 1993 proved that there were error-correcting codes with performance close to the theoretical limit and which can be used in industrial products. Quickly, turbo codes have been adopted in several standards such as DVB-RCS, UMTS, CDMA2000 and 3GPP-LTE. The increasing demand for high throughput applications in broadband applications until 1 Gb/s and beyond is strongly calling for high-speed turbo decoder implementations, thus leading to new challenges. An alternative approach was explored in this thesis : the decoding of error-correcting codes based on a stochastic representation of information. Principles of stochastic computation were first presented in the 1960’s as a method to carry out complex operations with a low hardware complexity. The main feature of this method is that the probabilities are converted into streams of random bits using Bernoulli sequences, in which the information is given by the statistics of the bits. As a result, complex arithmetic operations on probabilities are transformed into operations on bits using elementary logic gates. The application of stochastic calculation in iterative decoding of error-correcting codes leads to very simple physical structures of computation nodes. The objective of this thesis is to apply the stochastic decoding approach to the turbo codes. Our first contribution shows that a stochastic turbo decoder architecture can be obtained with no significant loss of performance. However, a major challenge in the implementation of stochastic turbo decoders is to improve the decoding throughput. In order to solve this challenge, we have proposed two efficient solutions : the transformation of stochastic additions into the exponential domain and the exploration of new parallelism schemes. The first technique consists in replacing the stochastic additions by simple operations after exponential transformations. This technique allows to reduce the computational complexity, and to improve the decoding throughput. The second technique is to represent a probability by several parallel stochastic streams. This method also allows us to compensate the correlation problem. These two techniques have resulted in stochastic convolutional decoders and turbo decoders with performances similar to the ones of conventional decoders. Finally, the proposed architectures for stochastic convolutional decoders and stochastic turbo decoders were implemented on programmable devices (FPGAs). The stochastic turbo decoder prototype demonstrates the feasibility of a stochastic turbo decoder in terms of performance and complexity. In addition, it enables many prospects for this alternative integration solution.